16 bit microprocessor

Introduction :

The INTEL 8086 was the first 16-bit microprocessor, it was developed using HMOS (high density short channel MOS) technology containing 29,000 transistor's housed in 40 pin DIP package. The 8086 does not have an internal clock circuit. The 8086 requires an external asymmetric clock source with 33% duty cycle. In this chapter we will study features, architecture and addressing modes of 8086 and 8088.

Feature of  8086:

1. The 8086 is a 16-bit microprocessor. The term "16-bit" means that its arithmetic logic unit, internal registers and most of its instructions are designed to work with 16-bit binary words. 2. The 8086 has a 16-bit data bus, so it can read data from or write data to memory and I/O ports either 16-bits or 8-bits at a time.

3. The 8086 has a 20-bit address bus, so it can directly access 220 or 1048576 (1 MB) memory locations. Each of the 1048576 memory location is byte (8-bit) wide. Therefore, a sixteen bit word is stored in two consecutive memory locations.

4. The 8086 can generate 16-bit I/O address, hence it can access 216 = 65536 I/O ports,

5. The 8086 provides fourteen 16-bit registers.

6. The 8086 has multiplexed address and data bus which reduces the number of pins needed, but does slow down the transfer of data (draw back).

7. The 8086 requires one phase clock with a 33% duty cycle to provide optimized internal timing as shown Fig. 4.1. It requires 5 MHz clock range. 

8. With 8086 it is possible to perform bit, byte, word and block operations. It performs the arithmetic and logical operations on bit, byte, word and decimal numbers including multiply and divide.. 

9. The Intel 8086 is designed to operate in two modes, namely the minimum mode and the maximum mode. When only one 8086 microprocessor is to be used in a microcomputer system, the 8086 is used in the minimum mode of operation, In this mode the microprocessor issues the control signal required by memory and I/O devices. In multiprocessors (more than one processor in the system) system 8086 operates in maximum mode. In maximum mode, the control signal are generated with the help of internal bus controller (8086). 

Fig: 1 clock cycle

10. The Intel 8086 supports multiprogramming. In multiprogramming, the code for two or more processes is stored in memory at the same time and is executed in a time-multiplexed fashion.

11. An interesting feature of the 8086 is that it fetches up to six instruction bytes from memory and queue stores them in order to speed up instruction execution.

Architecture of 8086:

The functional block diagram of the 8086 is shown in Fig.2 The Architecture of 8086 can be divided in two units. These are Bus Interface Unit (BIU) and Execution Unit (EU). These two functional units can work simultaneously to increase system speed and hence the throughput. Throughput is a measure of instruction executed per unit time.

Fig: 2 Architecture of 8086

Bus Interface Unit (BIU):

The bus interface unit is the 8086 interface to the outside world. It provides full 16-bit bidirectional data bus and 20-bit address bus. The bus interface unit is responsible for performing all external bus operations as listed below.

Functions of Bus Interface Unit:

1. It sends address of the memory or I/O.

2. It fetches instruction from memory.

3. It reads data from port/memory.

5. It supports instruction queuing.

4. It writes data into port/memory.

6. It provides the address relocation facility.

To implement these functions the BIU contains the instruction queue, segment registers, instruction pointer, address summer and bus control logic.

Instruction Queue: To speed up program execution, the BIU fetches six instruction bytes ahead of time from the memory. These prefetched instruction bytes are held for the execution unit in group of registers called Queue. With the help of queue it is possible to fetch next instruction when current instruction is in execution. The BIU is fetching and storing the instructions in the queue. The queue operates on the principle of first in first out (FIFO). So that the execution unit gets instruction for execution in the order they are fetched. The size of queue is 6 bytes for 8086 processor. The BIU fetches instruction code from memory and stores in queue. The Execution Unit (EU) fetches instruction codes from the queue for execution.

Execution Unit (EU):

Execution Unit consists of the following functional units. 

1. Control circuitry and Instruction Decoders.

2. Arithmetic and Logic Unit (ALU)

3. Flag register

4. General purpose registers

5. Stack Point Register and

6. Pointer and Index register.

Execution Unit (EU) works in parallel with BIU which informs the BIU about the location at which the next instruction or data is to be fetched. The phases of execution of the instruction are fetch, decode, execute and write. The fetch phase performs fetching of the instruction from the instruction queue. The decode phase performs the decoding of instruction. The execute phase performs operations on the data. The write phase performs the operation of storing the result at destination. The Execution Unit responsible for

● the execution of all instructions

● providing address to the BIU for fetching data/instruction and

● manipulating various registers as well as the flag register.

Control Circuitry and Instruction Decoder:

Control circuit of the EU directs all the internal operations of the processor. The instruction in the EU translates the instruction fetched from the memory into a series of actions carried out by the execution Unit.

Arithmetic and Logic Unit:

Arithmetic and Logic Unit performs 8-bit or 16-bit mathematical operations such as addition, subtraction, multiplication, division, data conversion and logical operations like logical NOT, OR or AND. It also performs register increment, decrement, and shift operation.

Register Organization of 8086:

8086 has a set of registers known as general purpose and special purpose registers. All of them are 16-bit registers. The general purpose registers can be used as either 8-bit registers or 16-bit registers. They may be either used for holding data, variables and intermediate results temporarily or other purposes like counter or for storing offset address of some particular addressing modes etc. The special purpose registers are used as segment register pointers, index registers or as offset storage registers for particular addressing modes.

General Data Registers:

Figure 3 shows the register organization of 8086. The registers AX, BX, CX and DX are the general purpose 16-bit registers. AX is used as 16-bit accumulator, with the lower 8-bits of AX designated as AL and higher 8-bits as AH. AL can be used as an 8-bit accumulator for 8-bit operations. This is the most important general purpose register having multiple functions.

fig:3  Register organization of 8086

Usually the letters H and L specify the higher and lower bytes of particular register. For example CH means the higher 8-bits of the CX register and CL means the lower 8-bits of the CX register. The letter X is used to specify the complete 16-bit register. The register CX is also used as default counter in case of string and loop instructions. The BX register is used as an offset storage for forming physical addresses in case of certain addressing modes. DX register is a general purpose register which may be used as an implicit operand or destination in case of a few instructions.

Segment Registers:

The physical address of the 8086 is 20-bit wide to access 1-Mbyte location. However, its registers and memory locations which contain logical address are just 16-bits wide. Here 8086 uses memory segmentation. It treats the 1-M byte of memory as divided into segments, with a maximum size of a segment as 64 Kbytes. The 8086 allows only four active segments. The 16 bit segment registers are provided within BIU or the 8086. These four registers are .

1. Code Segment (CS) register
2. Data Segment  (DS) register
3. Stack Segment (SS) register
4. Extra Segment (ES) register

These are used to  hold the upper 16-bit of the starting addresses of the four memory segment as shown in fig: 3 on which 8086 works at a particular time. For example the value in CS identifies the starting address of the 64-byte segment known as code segment. By starting address we mean the lowest addressed byte in the active code segment known. The starting address is also known as base address or segment base.

Fig:4 Memory segment

The BIU always inserts zeros for the lowest 4-bits (nibble) in the contents of segment register to generate 20-bit base address. For example, if the code segment register contains 348AH, then code segment will start at address 348A0H.

Function of Segment Registers:

1). The CS register holds the upper 16-bits of the starting address of the segment from which the BIU is currently fetching the instruction code byte.

2). The SS register is used for the upper 16-bits of the starting address for the program stack (all stack related instructions will operate on stack). 

3). The ES register and DS register are used to hold the upper 16-bit of the starting address of the two memory segments which are used for data.

Instruction Pointer:

The instruction pointer register holds the 16-bit address of the next code byte within the code segment. The value contained in the IP is referred to as an offset. This value must be offset from (added to) the segment base address in CS to produce the required 20-bit physical address. The Instruction pointer is also called as the program counter in other microprocessors.

Generation of 20-bit Address:

The contents of the CS register are multiplied by 16 le, shifted by 4 position to the left by inserting 4 zero bits and then the offset e. the contents of IP register are added to shifted contents of CS to generate physical address. As shown in Fig. 4 the contents of CS register are 348AH, therefore the shifted contents of CS register are 348A0H. When the BIU adds the offset of 4214H in the IP to this starting address, the result is 20-bit physical of 38AB4H.

fig: 5